- Departments / Centres
To understand the basic building blocks, logic gates, adders, multipliers, shifters and other digital devices
To apply logic minimization techniques, including Karnaugh Maps
To learn techniques and tools for programmable logic design
Unit – I
Review of Combinational and Sequential logic design – Structural models of combinational logic – Propagation delay – Behavioral Modeling – Boolean equation based behavioral models of combinational logic – Cyclic behavioral model of flip-flop and latches – A comparison of styles for behavioral modeling – Design documentation with functions and tasks
Unit – II
Synthesis of Combinational and Sequential logic – Introduction to synthesis – Synthesis of combinational logic – Synthesis of sequential logic with latches – Synthesis of three-state devices and bus interfaces – Synthesis of sequential logic with flip-flops – Registered logic – State encoding – Synthesis of gated clocks and clock enables – Anticipating the results of synthesis – Resets – Synthesis of loops – Design traps to avoid – Divide and Conquer: partitioning a design.
Unit – III
Design and Synthesis of Datapath Controllers – Partitioned sequential machines – Design example: Binary counter – Design and synthesis of a RISC stored-program machine – Processor, ALU, Controller, Instruction Set, Controller Design and Program Execution – UART – Operation, Transmitter, Receiver.
Unit – IV
Programmable logic devices – Storage devices – Programmable Logic Array (PLA) – Programmable Array Logic (PAL) – Programmability of PLDs – Complex PLDs – Introduction to Altera and Xilinx FPGAs – Algorithms – Nested loop programs and data flow graphs – Design Example of Pipelined Adder, Pipelined FIR Filter – Circular buffers – FIFOs and Synchronization across clock domains – Functional units for addition, subtraction, multiplication and division – Multiplication of signed binary numbers and fractions.
Unit – V
Postsynthesis Design Validation – Postsynthesis Timing Verification – Elimination of ASIC Timing Violations – False Paths – Dynamically Sensitized Paths – System Tasks for Timing Verificaion – Fault Simulation and Testing – Fault Simulation – Fault Simulation with Verifault-XL, lab exercises using Xilinx and Bluespec
Students understand the use standard digital memory devices as components in complex subsystems
Technical knowhow to design simple combinational logic circuits and logic controllers
Acquire skill set to develop the necessary software for basic digital systems
Michael D. Ciletti, "Advanced Digital Design with the VERILOG HDL, 2nd Edition, Pearson Education, 2010.
Samir Palnitkar "Verilog HDL", 2nd Edition, Pearson Education, 2003.
Stephenbrown, "Fundamentals of Digital Logic with Verilog", McGraw-Hill-2007.