Publications

Patents

Two patent applications were filed with the National Patent Office in September 2002:

  • G. Lakshminarayanan, B. Venkataramani, “Field Programmable Gate Array (FPGA) based Pipelined Array Multiplier” (OPARAM), Application No. 886/DEL/2002 dated 29-8-2002; Receipt No. 888 CBR No.2947
  • G. Lakshminarayanan, B. Venkataramani, “Field Programmable Gate Array (FPGA) based Wave Pipelined Array Multiplier (WPARAM)”, Application No. 885/DEL/2002 dated 29-8-2002; Receipt No. 887 CBR No.2947

Journal Papers

Sl. No.:

              Publication details

International

National

1.       

Journal Papers(SCI)

14

2

2.       

Journal Papers(Non SCI)

12

-

 

International Journals (SCI only):

  1. Lakshminarayanan, B. Venkataramani (2005), “Optimization techniques for FPGA based wave pipelined DSP blocks”, IEEE trans. on VLSI systems, Vol.13, No. 7, pp. 783-793.
  2. Seetharaman, B. Venkataramani and G. Lakshminarayanan, (2008) “Design and   FPGA   implementation of self-tuned   wave-pipelined   filters with   Distributed Arithmetic Algorithm”, Springer, Research journal on circuits, systems and signal processing, June 2008, Volume 27, Issue 3, pp. 261-276.
  3. Seetharaman, B. Venkataramani and G. Lakshminarayanan, (2008) “Automation techniques for implementation of Hybrid wave-pipelined 2D DWT”, Springer, Journal on Real-Time Image Processing, Volume 3, No: 3, PP 217-229, Springer-Verlag.
  4. Seetharaman, B. Venkataramani and G. Lakshminarayanan, (2008) “VLSI implementation of Hybrid wave-pipelined 2D DWT using lifting Scheme”, Hindawi Publishing Corporation, Journal on VLSI, Volume 2008 Issue 4. http://dx.doi.org/10.1155/2008/512746
  5. Vennila, G.Lakshminarayanan, Seok-Bum Ko, (2011) "Dynamic Partial Reconfigurable FFT for OFDM based Communication Systems", Circuits Systems and Signal Processing, Springer Verlog. DOI: 10.1007/s00034-011-9367-9.Online First™, 27 October. June 2012, Volume 31, Issue 3, pp 1049-1066
  6. Santhi, Siddharth Sarangan, K. Murali & G. Lakshminarayanan (2012): Performance analysis of pseudo 4-phase dual-rail asynchronous protocol, International Journal of Electronics, Taylor & Francis, Taylor & Francis, DOI:10.1080/00207217.2011.653949. Published online: 14 Mar 2012. Vol 99, Issue 8, 1101-1113
  7. Vennila, Alokkumarpatel, G.Lakshminarayanan, Seok-Bum Ko, “Dynamic Partial Reconfigurable Viterbi decoder for wireless standards”, Computer and Electrical Engineering, CAEE, Elsevier, Volume 39, Issue 2, February 2013, Pages 164–174.
  8. Swaminathan, G. Lakshminarayanan, Seok-Bum Ko, “Design and Verification of an Efficient WISHBONE-based Network Interface for Network on Chip” Elsevier Journal of Computers & Electrical Engineering, Volume 40, Issue 6, August 2014, Pages 1838–1857.
  9. Nithish Kumar Venkatachalam ; Lakshminarayanan Gopalakrishnan ; Mathini Sellathurai, “Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios”, IET Computers & Digital Techniques, DOI: 10.1049/iet-cdt.2015.0070, Vol. 10, Issue 2, pp. 56-68, March 2016
  10. Antony Xavier Glittas, Mathini Sellathurai, and G Lakshminarayanan, “A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO” IEEE Trans. On VLSI , 2016 (10.1109/TVLSI.2015.2504391)
  11. Antony Xavier Glittas, Mathini Sellathurai, and G Lakshminarayanan “Two-parallel Pipelined FFT Processors for Real-valued Signals” IET Circuits, Devices & Systems, Vol. 10, Issue 4, pp. 330-336, July 2016.
  12. S, Lakshminarayanan. G, “Reconfigurable address generator for multi-standard interleaver”, Microprocessors and Microsystems, Vol. 65, pp. 47-56, Mar. 2019.
  13. S, Lakshmi Renuka M, Lakshminarayanan. G, Mathini Sellathurai, “Low-complex processing element architecture for successive cancellation decoder”, Integration the VLSI Journal, Elsevier, 2019, DOI: 10.1016/j.vlsi.2019.01.005.
  14. Aravindhan Alagarsamy, Lakshminarayanan Gopalakrishnan, Seok Bum-Ko, “KBMA: A Knowledge Based Multi-objective Application Mapping Approach for 3D NoC”, IET Computers and Digital Techniques, 2019, DOI: 10.1049/iet-cdt.2018.5055.

National Journals (SCI only):

  1. Santhi, G.Lakshminarayanan, B.Venkataramani, “Design and Implementation of Online Clock Skew Scheme based Asynchronous Wave-Pipelined Distributed Arithmetic Filters on FPGA”, IETE Journal of Research, Vol 58, Issue 6, Nov-dec 2012. pp. 494-500.

DOI: 10.4103/0377-2063.106759

  1. Lakshminarayanan, B.Venkataramani, and G.Seetharaman, (2006) “Design and FPGA implementation of self tuned wave pipelined filters”, IETE Journal of Research, New Delhi, Vol.52, No.4, pp281-286.

International Journals (Non SCI only):

  1. Seetharaman, B. Venkataramani, and G. Lakshminarayanan, (2005) “Design and FPGA implementation of wave pipelined lifting scheme for two level 2D-DWT, WSEAS Transactions on Circuits and Systems, Issue 10, Vol. 4, pp.1284-1291.
  2. Santhi, ArunKumar S, G S Praveen Kalish, Siddharth Sarangan, G. Lakshminarayanan, (2010) “A Novel Pseudo 4 Phase Dual Rail Asynchronous Protocol With Self Reset Logic & Multiple Reset”, International Journal of Computer Applications, Vol.1,Number 21, Article : 4.,pp-17-21.
  3. N. Prabakar, G. Lakshminarayanan, K. K. Anilkumar, (2010) “Design and implementation of an Asynchronous controller for FPGA based asynchronous systems” International Journal of Computer Applications, Vol.1. Issue 21, pp. 23-29
  4. N. Prabakar, G. Lakshminarayanan, K. K. Anilkumar, (2010) “Design and Implementation of an Asynchronous Controller for FPGA Based Biosignal Processing”, International Journal of Computer Applications (IJCA), 4(4):33–37.
  5. Santhi, G.Seetharaman, Roshan Silwal, G.Lakshminarayanan, "Design and Implementation of Asynchronous WP DA FIR Filter using Online Clock Skew Scheme", International Journal of Design, Analysis and Tools for Integrated Circuits and Systems (IJDATICS), 2011, ISSN : 2223523X
  6. s, Lakshminarayanan.g, MathiniSellathurai : “Wide band Spectrum Sensing using Window based Energy Detector for AWGN and Rayleigh channels” International Journal of Engineering Research & Technology (IJERT) ,Vol. 2, Issue 5,May 2013, pp. 91-96
  7. Swaminathan, G. Lakshminarayanan, Seok-Bum Ko: High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip. Journal of Low Power Electronics, Vol. 9, No.3, 2013, pp-322-331.
  8. Nithish Kumar V, Pani Prithvi Raj, Lakshminarayanan G, Mathini Sellathurai: Low Power and Area Efficient Carry Select Adder”. Journal of Low Power Electronics, Volume 10, Number 4, December 2014, pp. 593-601
  9. Nithish Kumar, Koteswara Rao Nalluri, G. Lakshminarayanan, Mathini Sellathurai: “An Improved Recongurable FIR Filter using Common Subexpression Elimination Algorithm for Cognitive Radio.” Journal of Low Power Electronics, Vol.11, No.2, June 2015. pp. 181-189.
  10. A, Shalini S, Lakshminarayanan. G, “Cluster Based Application Mapping Strategy for 2D NoC”, Journal of Procedia Technology, Elsevier Publications, Vol. 25, pp 505-512, Sep 2016, DOI:10.1016/j.protcy.2016.08.138
  11. Shalini S, Aravindhan. A, Lakshminarayanan. G, “A Case Study on Cluster Based Power Aware Mapping Strategy for 2D NoC” ICTCAT Journal of Microelectronics, pp. 315-322, Vol. 2 (4), Jan 2017, DOI:10.21917/ijme.2017.0055
  12. Meenu Anna George, Aravindhan. A, Lakshminarayanan. G, “Design of Five Port Priority Based Router with Port Selection Logic for NoC” ICTCAT Journal of Microelectronics, pp. 293-299, Vol.2 (4), Jan 2017, 10.21917/ijme.2017.0051

International National conference papers

  1. Lakshminarayanan, Boby Geroge, B. Venkataramani, A. Ramakalyan , (1998) “Neural Network controlled Shift Register Traffic Shaper for ATM Networks” ,pp 33 - 36 , vol.1, TENCON.
  2. Lakshminarayanan, B. Venkataramani, M. Sasitharan, K.P. Senthil Kumar, (2000) “Design and Implementation of FPGA based wavepipelined multiplier accumulators", Proc. of the International Conf. on Circuits, Control, Communication and Devices, ICCCD’ 2000, VOL. I, No.59, pp.265-268.
  3. Lakshminarayanan, B. Venkataramani, K.P. Senthil Kumar, M. Sasitharan, (2000) V.A. Kiran Kottapalli, "Design and implementation of FPGA based wave pipelined Fast Convolver", Proc. of the International Conf. TENCON 2000, Kuala Lumpur, Malaysia, VOL. III, No.212, pp. 212-217.
  4. Lakshminarayanan, B. Venkataramani, J. Senthil Kumar, A.K. Md. Yousuf, G. Sriram, (2003) “Design and FPGA Implementation of Image Block Encoders with 2D-DWT”, Proc. of the International Conf. TENCON 2003, India, SessionZ04, pp.1015-1019 ,Advanced DSP-II.
  5. Seetharaman, B. Venkataramani, and G. Lakshminarayanan, (2005) “Design and FPGA implementation of lifting scheme for 2D-DWT using wave pipelining, Proc. of the 5th Int. conf. on Signal processing, Computational Geometry & Artificial Vision, pp.53-60.
  6. Lakshminarayanan and T.N. Prabakar, (2007) “On-Board Verification of FPGA Based Digital Systems Using NIOS Processor (A methodology without Hook-Ups and I/O Cards)”, International Conference on Signal Processing, Communications and Networking, pp 596 – 598, ICSCN .
  7. N.Prabhakar, G.Lakshminarayanan, K.K.Anilkumar, (2008) “FPGA Based Asynchronous Pipelined Multiplier with intelligent delay controller”, IEEE SOC Design Conference, pp: I-304 - I-309.
  8. Santhi, Sowjanya Tungala, Balakrishna.C, G.Lakshminarayanan, (2009) “Asynchronous Pipelined MB-OFDM UWB Transceiver on FPGA” presented in IEEE TENCON, Singapore.
  9. Kumaran, M.Santhi, M.Srikanth, Narayana Srinivasan, M.Balaj,G.Lakshminarayanan, (2009) ”Transient Current Sensing Based Completion Detection with Event Separation Logic for High Speed Asynchronous Pipelines”, presented in IEEE TENCON.
  10. Santhi, G.Lakshminarayanan, R.Sundaram, N.Balachandar, (2009) “Synchronous Pipelined Two-Stage Radix-4 200Mbps MB-OFDM UWB Viterbi Decoder on FPGA”,  IEEE ISOCC.
  11. Santhi, Surya vamshi vardhan, Dr.G.Lakshminarayanan (2009) FPGA based Asynchronous Pipelined Viterbi Decoder using Two Phase Bundled-Data Protocol -, , IEEE, ISOCC.
  12. Santhi, G.Seetharaman, Roshan Silwal, G.Lakshminarayanan, (2010) “A Novel Online Clock Skew Control Circuit for Asynchronous Wave pipelining on FPGA”, selected for presentation in IEEE DATICS Futuretech’10, Busan, Korea.
  13. Sanjay G. Talekar, S. Ramasamy, G. Lakshminarayanan and B. Venkataramani (2009) “500MS/s 4-b time interleaved SAR ADC using novel DAC architecture” 1st Asia Symposium on Quality Electronic Design, pp 202-205.
  14. Sanjay G. Talekar, S. Ramasamy, G. Lakshminarayanan and B. Venkataramani (2009) “Low power 700MSPS 4-bit 2bit/step time interleaved SAR ADC in 0.18µm CMOS”, pp: 1 – 5, EDAS IEEE-RSM 2009 conference, Malaysia.
  15. Sanjay G. Talekar, S. Ramasamy, G. Lakshminarayanan and B. Venkataramani (2009) “A Low power 700MSPS 4-bit time interleaved SAR ADC in 0.18µm CMOS”, pp: 1 - 5 , Singapore, TENCON 2009.
  16. N. Prabakar, Dr. G. Lakshminarayanan and Dr. K.K. Anilkumar, (2007) “SOPC based Asynchronous Pipelined DCT with self testing capability”, accepted for presentation in the IEEE International Conference on Microelectronics - IEEE ICM-07, Cairo, Egypt.
  17. Vennila, G.Lakshminarayanan, ArpitRaj, Anandkrishnan, Santhosh, Mithun Reddy, Vijaykumar, (2010) “Design of Self-Reconfigurable Task-Scheduler to Implement Multi-Rate MB-OFDM UWB Wireless Systems”, 2010 Intl Conf on Electronic Devices, Systems and Applications (ICEDSA), pp-37-42, Kualalampur, Malaysia.
  18. Vennila Arasu, Alok Kumar Patel, Jaimil Upadhyay, G. Lakshminarayanan, and S. Ko, (2011) "High Speed Reconfigurable Viterbi Decoder for Wireless Standards," 15th International Workshop on Multimedia Signal Processing & Transmission, pp. 114-119, Jeonju,Korea.
  19. VennilaArasu, Satyashil Nagrale, G.Lakshminarayanan,(2011) “FPGA implementation of adaptive mode PAPR reduction for cognitive radio applications”, International Conference on Communication Systems and Network Technologies, pp. 444-448, Katra, Jammu.
  20. Santhi, G.Lakshminarayanan, Sowjanya Tungala, Balakrishna.C, (2009) “FPGA Based Asynchronous Pipelined OFDM for MB-OFDM UWB Application”, IEEE International Conference on Control, Automation, Communication and Energy Conservation (INCACEC), Tamilnadu, India, pp. 1-6.
  21. Santhi, G.Lakshminarayanan, Sowjanya Tungala, Balakrishna.C, (2009) “Design of Low Power Asynchronous Pipelined Systems with Input Change Detection Circuit”, IEEE International Conference on Control, Automation, Communication and Energy Conservation (INCACEC), pp. 1-6.
  22. Santhi, M.Shravan kumar, T.N.Prabhakar, Dr.G.Lakshminarayanan, (2008) “Design and Implementation of pipelined MB-OFDM UWB transmitter back end modules on FPGA” -, IEEE ICCCN, Karur, Tamilnadu.
  23. Santhi,S.Arunkumar, G.S.Praveen kalish, K.Murali, S.Siddharth, Dr.G.Lakshminarayanan (2008) “A modified radix - 24 SDF pipelined OFDM module for FPGA based MB-OFDM UWB system” IEEE ICCCN, Karur, Tamilnadu.
  24. Vennila Arasu, Puneet Hyanki , H.Lakshman Sharma, G.Lakshminarayanan, Moon Ho Lee , Seok-Bum Ko (2010) “PAPR Reduction For Improving Performance Of OFDM Systems”,   IEEE International Conference On Communication Control And Computing Technologies pp-77-82.
  25. Vennila, G.Lakshminarayanan, Sowjanya Tungala, (2009) “Design of Reconfigurable UWB transmitter to Implement Multi-Rate MB-OFDM UWB Wireless System”,
    Advances in Computing, Control, & Telecommunication Technologies, pp 411 - 413.
  26. Vennila, G.Lakshminarayanan, Balakrishna.C, (2010) “Design of Reconfigurable Multi-rate MB-OFDM UWB Wireless System” in the proceedings of 2010 IEEE International Conference On Computing Communication and Networking .
  27. N. Prabakar, G. Lakshminarayanan, K. K. Anilkumar,(2008) “SOPC Based Low Power Image Processor for Telemedicine Applications” IEEE International Conference on Biomedical Engineering, Singapore.
  28. Lakshminarayanan and T.N. Prabakar, (2007) “Design and Implementation of SOPC Based Asynchronous Pipelined DCT”, International Conference on Nanomaterials, Communication and Broadcasting Systems, SASTRA University, Thanjavur, TamilNadu.
  29. Lakshminarayanan and T.N. Prabakar, (2007) “Design and Implementation of Asynchronous Systems on Altera SOPC Environment”, International Conference on Advanced Computing and Communication, Sethu Institute of Technology, Kariapatti, TamilNadu.
  30. Deepa N Sarma, Lakshminarayanan,(2011) “Encoding scheme for reducing power dissipation in NOC serial links”, selected for CICN’2011, India.
  31. Deepa N Sarma, G. Lakshminarayanan,(2012) “A Novel Encoding scheme for Low Power in Network on Chip links” selected for International conference on VLSI Design, Hyderabad International Convention Centre, Hyderabad, January 7-11, 2012
  32. Vennila , Kumar Palaniappan CT, Kodati Vamsi Krishna, G.Lakshminarayanan, Seok-Bum Ko,(2012)   " Dynamic partial reconfigurable FFT/IFFT pruning for OFDM based Cognitive radio", paper accepted for ISCAS,Seoul,South Korea.
  33. Geethu S, Lakshminarayanan G, “A Novel High speed two stage detector for spectrum sensing” Second International Conference on Power, Control and embedded systems(ICPCES’12), December 17-19,2012, Allahabad,U.P India.
  34. Swaminathan, G. Lakshminarayanan, Frank Lang, Maher Fahmi, Seok-Bum Ko, "Design of a low power Network Interface for Network on Chip," ", (CCECE ’2013) IEEE Canadian conf. electrical and computer engg. 2013, Regina, Canada, May 2013
  35. Vennila, Suresh.K, Rohit Rathor, G.Lakshminarayanan and S. Ko, "Dynamic partial reconfigurable FFT/IFFT pruning for OFDM based Cognitive radio", (CCECE ’2013) IEEE Canadian conf. electrical and computer engg. 2013, Regina, Canada, May 2013
  36. Nithish Kumar V, Venkat Reddy K, Geethu  S, Lakshminarayanan G, Mathini Sellathurai, “Reconfigurable hybrid spectrum sensing technique for cognitive radio” , Eighth IEEE International Conference on Industrial and Information Systems (ICIIS’2013), Srilanka, Dec. 17-20.
  37. Nithish Kumar V, Harsha Bhalavi Reddy K, Geethu  S, Lakshminarayanan G, Mathini Sellathurai, “FPGA based decision making engine for cognitive radio using genetic algorithm” , Eighth IEEE International Conference on Industrial and Information Systems (ICIIS’2013), Srilanka, Dec. 17-20.
  38. Geethu S, Lakshminarayanan G, “A Novel Selection Based Hybrid Spectrum sensing technique for cognitive radios” IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology (ICECCN 2013) Tuticorin, 25& 26th March 2013 Tamilnadu, India.
  39. X Antony Xavier Glittas and Lakshminarayanan G, “Pipelined FFT architectures for Real-time Signal Processing and Wireless Communication Applications,” 18th International Symposium on VLSI Design and Test (VDAT 2014), Coimbatore, July, 2014
  40. Nithishkumar V, Koteswara Rao Nalluri and Lakshminarayanan G, “Design of Area and Power Efficient Digital FIR Filter Using Modified MAC Unit”, Accepted for publication in 2nd International Conference on Electronics & Communication Systems, Coimbatore, February 2015.
  41. Kokila Bharti Jaiswal, Nithish Kumar V, Pavithra Seshadri and Lakshminarayanan G, "Low Power Wallace Tree Multiplier using modified Full Adder", 3rd International Conference on Signal Processing, Communication and Networking (ICSCN), Chennai, 26-28 March 2015.
  42. Ishwerya, P., V. Nithish Kumar, and G. Lakshminarayanan (2016), An efficient digital baseband encoder for short range wireless communication applications. International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), pp. 2775-2779, 3-5 March 2016.
  43. Aravindhan Alagarsamy, Lakshminarayanan G, “ SAT: A New Application Mapping Method for Power Optimization in 2D-NoC”, 20th International Symposium on VLSI Design and Test (VDAT), 24-27 May 2016.
  44. Ishwerya, P., S. Geethu, and G. Lakshminarayanan (2016), Autocorrelation based spectrum sensing architecture on FPGA with dynamic offset compensation. 2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), pp. 153-157, 13-14 Aug. 2016.
  45. Ishwerya, P., S. Geethu, and G. Lakshminarayanan, An efficient hybrid spectrum sensing architecture on FPGA. 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 22-24 March 2017.
  46. Kartikeya Dubey, Marshal Raj, G. Lakshminarayanan, " QCA Code converters using Novel Fault and Area efficient Exclusive-OR gate", International Conference on Nanotechnology: Ideas, Innovations and Initiatives, Roorkee, Dec 2017.
  47. Kartikeya Dubey, Marshal Raj, G. Lakshminarayanan, "Design Of Majority Logic Based Comparator", IEEE 9th International Conference on Computing Communication and Networking Technologies (ICCCNT), Bengaluru, July 2018.
  48. Rejil Raj E P, Bibin Sam Paul, G Lakshmi Narayanan, "Simplified SIFT Histogram Of Oriented Gradients Bin Locator In FPGA," IEEE 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Bengaluru, July 2018.
  49. S, Lakshminarayanan. G, “Low-Complexity Successive Cancellation Decoder with Scan Chain”, IEEE International Conference on Circuits and Systems in Digital Enterprise Technology (ICCSDET), Kerala, Dec 21 - 22, 2018.
  50. R, Lakshminarayanan. G, “Design and defect analysis of novel NAND/NOR gate in Quantum-dot cellular automata”, IEEE International Conference on Circuits and Systems in Digital Enterprise Technology (ICCSDET), Kerala, Dec 21 - 22, 2018.
  51. Aravindhan Alagarsamy and Lakshminarayanan Gopalakrishnan, “MBA: A New Cluster Based Bandwidth and Power Aware Mapping for 2D NoC”, IEEE International Conference on Circuits and Systems in Digital Enterprise Technology (ICCSDET), Kerala, Dec 21 - 22, 2018.

National conference papers

  1. Maheswari and Dr.G.Lakshminarayanan, (2011) "Novel protocol for enhancing the speed of dynamic spectrum sensing in cognitive radio", Fourth National Conference on Digital Convergence, pp: 5-9.
  2. Vennila, G. Lakshminarayanan and Padma Bhargavi, ,(2007) “Design and FPGA Implementation of High Speed Filters Using Wave Steering Technique” National Conference, Alagappa Chettiar College of Engineering, Karaikudi.
  3. Seetharaman, B. Venkataramani, and G. Lakshminarayanan, (2005) “Design and FPGA implementation of wavepipelined image block encoders using 2D-DWT”, Proceedings of VLSI Design and Test symposium VDAT 2005, Bangalore,pp. 12-20.
  4. Seetharaman, G. Lakshminarayanan, B. Venkataramani, (2004) “Design and FPGA implementation of wavepipelined Distributed Arithmetic based filters”, Progress in VLSI Design and Test 2004, pp. 216-220 Mysore.
  5. Lakshminarayanan, B. Venkataramani, M. Yousuff Sheriff, T. Rajavelu, M. Ramesh,(2004) “Self tuning circuit for FPGA based wavepipelined multipliers”, Proceedings of VLSI Design and Test workshop VDAT 2004, Mysore, pp. 93-101
  6. Senthil Kumar, G. Lakshminarayanan, B. Venkataramani, G. Sriram, M.S. Jambunathan,(2003.) “Design and Implementation of FPGA based Fast Multipliers with Optimum Placement and Routing using Structure Organizer”, National Conference on emerging trends in VLSI design and testing, India.
  7. Uma Maheswari, H. Anand, S. Ramasamy, K. Subramanyam, B. Venkataramani, G. Lakshminarayanan,(2003) “Performance Evaluation of Various Schemes for FPGA Implementation of 2D-DWT”, National Conference on Emerging Trends in VLSI Design and Testing, India.
  8. Balaji, B. Venkataramani, M. Bhaskar, G. Lakshminarayanan, (2001) “Enhancing the Performance of the TI DSP systems with FPGAs”, Texas Instruments DSPFEST-2001, Bangalore.