Research Supervision

UG Project

  1. FPGA Implementation of Adaptive filter, 2022
  2. Home automation and energy management system using FPGA, 2022
  3. Occluded face recognition with deep learning and edge application, 2021
  4. FPGA Implementation of 64-bit MDCLCG using High-Speed Area-Efficient Three Operand Binary Adder, 2021
  5. FPGA implementation of Fast Fourier transform for heart rate estimation from photoplethysmogram(PPG) signals, 2020
  6. Study and performance analysis of 5G NR RF transmitter, 2020
  7. Design of RF mixer with high linearity and low power for 5G Applications, 2019
  8. Design of RF Front-end receiver for 5G IoT applications with linearity improvement, 2019
  9. Implementation of CRC architecture in FPGA, 2018
  10. Stress detection and analysis using physiological sensors, 2018
  11. Non-invasive blood glucose level monitoring using laser spectroscopy, 2018
  12. Implementation of digital hearing aid using ski slope frequency shaper, 2017
  13. Sensor finger printing for mobile identification, 2017
  14. Design and implementation of 32-bit RISC processor in FPGA, 2016
  15. Mobile based biometric IRIS recognition system, 2016
  16. V-set cache design for the last level cache (LLC) of multi-core microprocessor, 2016
  17. Pest detection using sensors, 2015
  18. Pest detection using image processing, 2015
  19. Automatic automobile headlight intensity control for mountain terrain, 2014
  20. Smart robust real time automatic headlight control system, 2014
  21. Design of a speech recognition system for isolated word detection, 2009
  22. Implementation of code division multiple access (CDMA) system in `C6X architecture, 2009
  23. Design and implementation of asynchronous serial interconnect link, 2009
  24. Microcontroller based digital odometer and tachometer, 2007
  25. Data acquisition unit for TMS320C50, 2005
  26. Simulation of background noise suppression in speech signal, 2001

UG Internships (other Institutions)

  1. Institute internship – FPGA Implementation of pre-processing block for heart rate estimation using PPG signals, 2019.

2. AICTE-Margdarshan scheme – Algorithm Implementation of pre-processing block for heart rate estimation using PPG signals, 2019.

PG Project

  1. Design and verification of AXI data path width compressor IP and AXI-APB bridge IP, 2022.
  2. Design and Implementation of Unity gain zero offset CMOS Buffer for 14-bit SAR ADC in SCL 180nm Technology 2022.
  3. Design and implementation of Bootstrap Switch circuit for 14-bit SAR ADC in SCL 180nm Technology 2022.
  4. Design of 4-6GHz wideband single-ended to differential-ended LNA for IEEE 802.11ax wireless applications, 2020.
  5. NAND Flash Memory Operation and Verification, 2020
  6. Direct Digital Synthesizer (DDS) for digital modulation, 2020.
  7. A wide band low power low noise amplifier with input series peaking for 0.5 to 3.5 GHz applications, 2019
  8. Active inductor based bandpass filter design for 2.4GHz RF Transceiver, 2019.
  9. Low power low noise inductor less LNA at 2.4GHz, 2019
  10. A 4-6GHz low noise amplifier for 5G applications, 2019
  11. A study of the linearity performance of RF mixer using psedudo-sine wave as local oscillator, 2018
  12. Design and implementation of mixer for 2.4GHz WPAN receiver, 2018
  13. Carrier synchronization of 2.4GHz transceiver using COSTAS loop, 2018
  14. Design of bandpass filter for 2.4GHZ wireless transceiver, 2018
  15. Design of two stage Class-E cascade power amplifier at 2.4GHz with active feedback, 2018
  16. Design and implementation of band pass filter for 2.4GHz wireless transceiver,2017
  17. Coverage enhancement for directed error injection,2017
  18. A wideband inductor less LNA with local feedback and noise cancellation for low power applications, 2017
  19. Design of class-E power amplifier for wireless transceiver, 2017
  20. Design and implementation of 2.4GHz power amplifier in 130nm technology, 2016
  21. Low frequency front end codec design for 2.4GHz wireless transceiver         , 2016
  22. Design of low pass filter and variable gain amplifier for 2.4GHz on-chip wireless transceiver , 2016
  23. Design and implementation of 2.4GHz local oscillator for on-chip transceiver in 130nm technology, 2016
  24. Design and implementation of 2.4GHz low noise amplifier, 2016
  25. Design of mixer for 2.4GHz low power wireless applications, 2016
  26. Design of high speed delay locked loop (DLL) for on-chip serial interconnect transceivers, 2015
  27. Design of active inductor for quasi-resonant interconnect, 2015
  28. Bi-directional differential on-chip wave pipelined serial interconnect with surfing, 2015
  29. Design of high speed low power 64-bit transmitter and design of synchronizer for transceiver , 2015
  30. Low power interconnect signaling using differential keying and PWM encoding, 2015
  31. Design and implementation of surfing scheme for wave pipelined differential serial interconnect using repeater insertion in 180nm and 90nm technology, 2014
  32. Design of differential transceiver for on-chip serial interconnect based on method of logical effort, 2014
  33. Implementation of synchronizer for on-chip transceiver in 55nm technology, 2014
  34. Design of high speed delay locked loop (DLL) for on-chip serial interconnect transceiver, 2014
  35. Design of active inductor using resistive feedback technique for quasi-resonant interconnects, 2014
  36. Design of dynamic self-controllable inverter pair using surfing technique in 180nm and 90nm technology,      2013
  37. Design of differential transmitter for on-chip serial interconnect based on method of logical effort, 2013
  38. Design of low power active inductor using resistive feedback technique for quasi-resonant interconnects, 2013
  39. Design of high speed DLL for on-chip serial interconnect transceivers, 2013
  40. Implementation of a test chip for on-chip serial interconnect transceiver, 2013
  41. Design and implementation of wave pipelined differential serial interconnect with surfing scheme using method of logical effort, 2012
  42. Design of high speed delay locked loop (DLL) for on-chip serial interconnect transceivers, 2012
  43. Design of differential transmitter for on-chip serial interconnect based on method of logical effort, 2012
  44. Implementation of quasi-resonant interconnect serial link using active inductor, 2012
  45. Design of high speed low-power transmitter for on-chip differential serial interconnect, 2011
  46. Design and implementation of wave pipelined differential serial interconnect with surfing scheme, 2011
  47. Design and implementation of high speed low-power and area on-chip receiver for serial interconnect, 2011
  48. A low power, low latency tunable quasi-resonant interconnect using active inductor, 2011
  49. Implementation of ring oscillator and random data generator for on-chip synchronous serial interconnect, 2010
  50. Implementation of multi-phase DLL for on-chip synchronous interconnect, 2010
  51. Implementation of transmitter for on-chip serial interconnect, 2010
  52. Implementation of active inductor to obtain quasi-resonance in  interconnect serial link, 2010
  53. Implementation of high-speed multi-phase DLL for on-chip synchronous interconnect, 2009
  54. Implementation of asynchronous transceivers using self-clocked method for high speed on-chip interconnects, 2009
  55. Current mode interconnect system with synchronized transmitter and receiver, 2009
  56. Implementation of current mode Quasi-resonant interconnects, 2009
  57. Implementation of receiver for a far end interconnect, 2009
  58. Delay estimation of hybrid current/voltage mode repeater for on-chip interconnects in deep submicron CMOS, 2008
  59. Implementation of wide band voltage and current mode receiver for on-chip global interconnects in deep submicron CMOS technology, 2008
  60. Implementation of current mode transmitter for on-chip global interconnects in deep submicron CMOS technology, 2008
  61. Modeling interconnect as coplanar waveguide technology, 2008
  62. Simulation and analysis of hybrid current/voltage mode repeater for on-chip interconnects in deep submicron CMOS, 2007
  63. Global interconnect width optimization for latency and bandwidth, 2007
  64. Implementation of an all-digital Phase Locked Loop, 2007
  65. FPGA implementation of RC5 IR remote control decoder using RISC Microcontroller, 2004
  66. Implementation of 2D-DCT using Spartan FPGA, 2003
  67. Joint Source channel coding in digital communication systems, 2003
  68. MPEG 1 layer 1 encoding implementation in FPGA, 2003
  69. Digital Voice echo cancellation implementation on TMS320C54X, M.Sc. Applied Electronics, 2002

Doctor of Philosophy (Ph.D.)

 

S. No.

Name of the Scholar

Area of Research

Year of Joining and status

Funding

1

Archana S.

On-chip RF Antenna Design

2015 -2020 (Completed)

Institute

2

Chrisben Gladson S

On-chip Wireless Transceiver Design

2015-2020 (Completed)

DeitY

3

Arunkumar K R

Biomedical Signal Processing Algorithms

2016 -2020 (Completed)

DeitY

4

Lakshmi N.S.

On-chip RF filter design

2016 (Completed)

Institute

5

Banoth Santhosh Kumar

Low Power VLSI ASIC design

2017 (Pursuing)

Institute

6

Shubanjay S Pujari

FPGA Implementation of Hyperbolic CORDIC

2018 (Pursuing)

QIP

7

Thenmozhi. V

RF Front end design for 5G applications

2019(Pursuing)

Institute

8

Nivedha S

Analog VLSI Design

2019 (Pursuing)

Institute

9

Bellamkonda Srikanth

Network-on-chip (VLSI)

2019(Pursuing)

External (Part-time)

10

A Lakshmaiah

Processor Architecture

2019 (Pursuing)

External

(Part-time)