Electronics and Communication Engineering

Dr. Srinivasulu Jogi

Dr. Srinivasulu Jogi born in Nellore, Andhra Pradesh, India in 1986. He received his Ph.D degree in signal processing domain for the work “Stability Analysis of Nonlinear Digital Filters with External Interferenes” from Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram, Tamilnadu, India in 2021. He is currently involved in various teaching/research-related areas like Signal Processing, Nonlinear System Design, VLSI system design, and VLSI Signal Processing. He is a member of the IEEE. His research interests includes nonlinear system modeling and design, investigating the robust stability of delayed digital systems, and multi-dimensional systems.

Qualification

Ph.D. (2021), Signal Processing from Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram, Tamilnadu, India.
M. Tech (2009), First Class with Distinction in VLSI System Design from Sreenivasa Institute of Technology and Mangement Studies, Chittoor, Andhra Pradesh affiliated to Jawaharlal Nehru Technological University Ananthapur, Anathapur, Andhra Pradesh, India.
B. Tech (2007), First Class with Distinction in Electronics and Communication Engineering from NBKR Institute of Science and Technology, Nellore Andhra Pradesh affiliated to Sri Venkateswara University Tirupati, Tirupati, Andhra Pradesh, India

Specialization

Signal Processing
VLSI

Research Credentials

Google scholar: https://scholar.google.com/citations?user=9IjuKfUAAAAJ&hl=en

ORCID: https://orcid.org/0000-0002-3922-9705

Scopus: https://www.scopus.com/authid/detail.uri?authorId=57200615940

Area of Expertise

Nonlinear system design
Robust stability
Delayed systems,
Multi-dimensional systems.
FPGA based system design

Professional Society Membership

IEEE Member (Member No: 97887451)

Employment Profile

Assistant Professor (Grade II, AGP-6000), Department of ECE, National Institute of Technology, Tiruchirapalli, Tamilnadu, from September 28, 2022 to till date.
Assistant Professor, Department of ECE, Priyadarshini College of Engineering and Technology, Nellore, Andhra Pradesh, from June 2010 to April 2016

Details of Academic Work

Department MIS Coordinator
Department NPTEl Coordinator
Department Academic Audit Committe Member
UG Admission Committee Member

Courses taught at Postgraduate and Undergraduate levels:

UG Level

Signals and Systems
Digital Signal Processing
Digital Logic Design
Microprocessors and Micro-controllers
Probability and Random Process

PG Level:

Advanced Digital Signal Processing
Low Power VLSI Circuits & Systems
Digital System Design

Participation in Workshops/ Symposia/ Conferences/ Colloquia /Seminars/ Schools etc.

Date (s)	Title of Activity	Level of Event	Role	Event Organized by	Venue
27-04-2015 to09-05-2015	FDP	National	Participant	AICTE	NBKR Institute of Science and Technology, Nellore, Andhra Pradesh
21-08-2015 to22-08-2015	Seminar	National	Participant	DST	DVR & DHS MIC College of Technology, Andhra Pradesh

Publications

Refereed Research Journals:

[J01] S. Jogi, M. Pulikonda, and P. Kokil, "Stability and Performance Analysis of Interfered Digital Systems with generalized Overfo Nonlinearities,” IFAC-PapersOnLine, Elsevier, vol. 57, pp. 339–344, 2024.

[J02] S. Jogi and P. Kokil, “An optimal H_infinity approach for local stability analysis of nonlinear digital systems with saturation nonlinearity and external interference,” Fluctuations and Noise Letters, vol. 21, no.5, October 2022.

[J03] P. Kokil, S. Jogi, C. K. Ahn, and H. Kar, “An improved local stability criterion for digital filters with interference and overflow nonlinearity,” IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 67, no. 3, pp. 595–599, 2020.

[J04] S. Jogi, C. G. Parthipan, and P. Kokil, “A passivity-based approach for digital filters subjected to external disturbance and nonlinearities,” IFAC-PapersOnLine, Elsevier, vol. 53, no. 1, pp. 428–434, 2020.

[J05] P. Kokil, S. Jogi, and C. K. Ahn, “Stability analysis of digital filters subjected to interference using generalized overflow nonlinearities,” Signal Processing, Elsevier, vol. 148, pp. 1–8, 2018.

[J06] P. Kokil, C. G. Parthipan, S. Jogi, and H. Kar, “Criterion for realizing state-delayed digital filters subjected to external interference employing saturation arithmetic,” Cluster Computing, Springer, vol. 22, no. 6, pp. 15187–15194, 2018.

[J07] P. Kokil, S. X. Arockiaraj, S. Jogi, and H. Kar, “New realizability criterion for digital filters with external disturbance and saturation arithmetic,” International Journal of Electronics and Communications (AEU), Elsevier, vol. 85, pp. 179–182, 2018

Conferences/Workshops/Symposia Proceedings

[C01] S. Jogi and P. Kokil, “Improved Hankel Norm Criterion for Interfered Nonlinear Digital Filters Subjected to Hardware Constraints,” in Proc. 27th IEEE National Conference on Communications (NCC), IIT Kanpur & IIT Roorkee. pp. 1–6, Jul. 2021, DOI: 10.1109/NCC52529.2021.9530092.

[C02] S. Jogi and P. Kokil, “Hankel norm for nonlinear digital systems with hardware limitations and external input,” in Proc. 26th IEEE National Conference on Communications (NCC), Kharagpur, pp. 1–6, Feb. 2020, DOI: 10.1109/NCC48643.2020.9056047

Invited Lectures and Talks Delivered

[1] Delivered an invited talk on "Recent Trends in Electronics and Communication - An Approach through AI, ML, and DL Techniques" during the faculty development program at NBKRIST, A.P., from May 22 to May 26, 2023.

[2] Delivered an invited talk on "Creative methods and tools for effective research dissemination" during the seven-day workshop under the Karyashala scheme (a SERB initiative) at IIITDM Kancheepuram Chennai from Dec 10 to Dec 16, 2022.

Workshops

[1] Karyashala (High-end workshop) on "System on Chip Design and FPGA Programming using Verilog", March 18^th to March 24^th, 2024

[2] Karyashala (High-end workshop) on "Hands-on Training on FPGA Architectures and Programming using Verilog HDL", June 05^th to June 11^th, 2023

Contact Address