Dr. Surya Teja Naga Srinivas Padala
Education
Ph.D. Electrical Engineering Department, Indian Institute of Technology Patna (2018-2023)
M.Tech. Microelectronics & VLSI of Electronics and Communication Engineering, NIT Durgapur (2012-2014)
B.Tech. Electronics and Communication Engineering, Affiliated to Jawaharlal Nehru Technological University Kakinada (2008-2012)
Professional Experience
(12/2025 to present) -> Assistant Professor, NIT-Tiruchirappalli, Tamilnadu
(08/2023 to 12/2025) -> Assistant Professor, VIT Vellore
(06/2015 to 12/2017) -> Assistant Professor, Vignan Institute of Information Technology Vizag
Publication
Geometry-Driven Thermal Noise Trends in GAA Nanowire Devices
Dielectric Modulation-Based High-Sensitivity Biomolecular Detection Using Ge/Si Heterostructure ES Fin-TFET Biosensors: A Detailed Performance Study
Computational investigation of trapezoidal channel profiles in Gate-All-Around (GAA) FETs for digital performance
Investigation of BTBT-Triggered Split-Gate Junctionless Nanosheet FETs for Analog and RF Applications
Impact of ambient temperature on CombFET for sub-5-nm technology nodes: An RF performance perspective
A machine learning approach to accelerate reliability prediction in nanowire FETs from self-heating perspective
Logic-in-memory application of silicon nanotube-based FBFET with core-source architecture
Impact of process-induced inclined side-walls on gate leakage current of nanowire GAA MOSFETs
Impact of self-heating on thermal noise in In1− xGaxAs GAA MOSFETs
Impact of process-induced inclined sidewalls on gate-induced drain leakage (GIDL) current of nanowire GAA MOSFETs
Physical insight into self-heating induced performance degradation in RingFET
Impact of Self-Heating on Linearity Performance of In0.53Ga0.47As-Based Gate-All-Around MOSFETs
Effect of self-heating on small-signal parameters of In0.53Ga0.47As based gate-all-around MOSFETs
Back Bias Induced Modeling of Subthreshold Characteristics of SOI Junctionless Field Effect Transistor (JLFET)
Threshold Voltage Modeling of tri-Gate Schottky-Barrier (TGSB) Field-Effect-Transistors (FETs)
Self-heating effects and hot carrier degradation in In0.53Ga0.47As gate-all-around MOSFETs
Thermal noise models for trigate junctionless transistors including substrate bias effects
An insight into self-heating effects and its implications on hot carrier degradation for silicon-nanotube-based double gate-all-around (DGAA) MOSFETs
Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET)