EC802

Modeling and Synthesis with  Verilog HDL    3-0-0-3

COURSE OBJECTIVES

  • To design combinational, sequential circuits using Verilog HDL.
  • To understand  behavioral and RTL modeling of digital circuits
  • To verify that a design meets its timing constraints, both manually and through the use of computer aided design tools
  • To simulate, synthesize, and program their designs on a development board
  • To verify and design the digital circuit by means of Computer Aided Engineering tools which involves in programming with the help of Verilog HDL.

 

COURSE CONTENT

Hardware  modeling  with  the  verilog  HDL.  Encapsulation,  modeling  primitives,  different  types  of description.

Logic system, data types and operators for modeling in verilog HDL. Verilog Models of propagation delay and net delay path delays and simulation, inertial delay effects and pulse rejection.

Behavioral descriptions in verilog HDL. Synthesis of combinational logic.

HDL-based synthesis - technology-independent design, styles for synthesis of combinational and sequential logic, synthesis of finite state machines, synthesis of gated clocks, design partitions and hierarchical structures.

Synthesis  of  language  constructs,  nets,  register  variables,  expressions  and  operators,  assignments  and compiler directives. Switch-level models in verilog. Design examples in verilog.

 

Text Books

1.   M.D.Ciletti, “Modeling, Synthesis and Rapid Prototyping with the Verilog HDL”, PHI, 1999.

2.   S. Palnitkar, “Verilog HDL – A Guide to Digital Design and Synthesis”, Pearson, 2003.

 

Reference Books

1.   J Bhaskar, “A Verilog HDL Primer (3/e)”, Kluwer, 2005.

2.   M.G.Arnold, “Verilog Digital – Computer Design”, Prentice Hall (PTR), 1999.

 

COURSE OUTCOMES

Students are able to

CO1: understand the basic concepts of verilog HDL

CO2: model digital systems in verilog HDL at different levels of abstraction

CO3: know the simulation techniques and test bench creation.

CO4: understand the design flow from simulation to synthesizable version

        CO5: get an idea of the process of synthesis and post-synthesis