- Departments / Centres
· To make the students exposed to Front end and Back end VLSI CAD tools.
An overview of OS commands. System settings and configuration. Introduction to UNIX commands.
Writing Shell scripts. VLSI design automation tools. An overview of the features of practical CAD tools. Modelsim, Leonardo spectrum, ISE 13.1i, Quartus II, VLSI backend tools.
Synthesis and simulation using HDLs-Logic synthesis using verilog and VHDL. Memory and FSM synthesis. Performance driven synthesis, Simulation- Types of simulation. Static timing analysis. Formal verification.Switch level and transistor level simulation.
Circuit simulation using Spice: Circuit description.AC, DC and transient analysis. Advanced spice commands and analysis. Models for diodes, transistors and opamp. Digital building blocks.A/D, D/A and sample and hold circuits. Design and analysis of mixed signal circuits.
System Verilog- Introduction, Design hierarchy, Data types, Operators and language constructs. Functional coverage, Assertions, Interfaces and test bench structures.
Mixed signal circuit modeling and analysis, Concept of System on chip. Introduction to Cypress Programmable System on Chip (PSoC). Structure of PSoC, PSoC Designer, PSoC Modules, Interconnects, Memory Management, Global Resources, and Design Examples.
1. M.J.S.Smith, “Application Specific Integrated Circuits”,Pearson, 2008.
2. M.H.Rashid, “Introduction to PSpice using OrCAD for circuits and electronics”, Pearson, 2004.
3. S.Sutherland, S. Davidmann, P. Flake, “System Verilog For Design”,(2/e), Springer,2006.
1. Z. Dr Mark, “Digital System Design with System Verilog “,Pearson, 2010.
2. Robert Ashby, “Designer's Guide to the Cypress PSoC,Newnes (An imprint of Elsevier)”, 2006
3. O.H. Bailey, “The Beginner's Guide to PSoC”, Express Timelines Industries Inc.
Students are able to
CO1: understand the special features of VLSI back end and front end CAD tools and Unix shell script
CO2: write synthesizable verilog and VHDL code.
CO3: write Pspice code for any electronics circuit and to perform monte-carlo analysis and sensitivity/worst case analysis.
CO4: understand the difference between verilog and system verilog and are able to write system verilog code.
CO5: understand Cypress PSOC structure, modules and interconnects.