An overview of DSP concepts, Representations of DSP algorithms. Loop bound and iteration bound.
Transformation Techniques: Retiming, Folding and Unfolding
Pipelining of FIR filters. Parallel processing of FIR filters. Pipelining and parallel processing for low power, Combining Pipelining and Parallel Processing. Systolic Architecture Design
Pipeline interleaving in digital filters. Pipelining and parallel processing for IIR filters. Low power IIR filter design using pipelining and parallel processing, Pipelined adaptive digital filters.
Synchronous pipelining and clocking styles, clock skew and clock distribution in bit level pipelined VLSI designs. Wave pipelining, constraint space diagram and degree of wave pipelining, Implementation of wave- pipelined systems, Asynchronous pipelining.
1. K.K.Parhi, “VLSI Digital Signal Processing Systems”, John-Wiley, 2007
1. U. Meyer -Baese,” Digital Signal Processing with FPGAs”, Springer, 2004
2. W.Burleson, K. Konstantinides, T.H. Meng,” VLSI Signal Processing””,1996.
3. R.J. Higgins, “Digital signal processing in VLSI”, 1990.
4. S.Y.Kung, H.J. Whitehouse, “VLSI and modern signal processing”, 1985
Students are able to
CO1: understand the overview of DSP concepts
CO2: improve the speed of digital system through transformation techniques.
CO3: perform Pipelining and parallel processing in FIR systems to achieve high speed and low power.
CO4: perform Pipelining and parallel processing in IIR systems and adaptive filters
CO5: understand clocking issues and asynchronous system
