National conferences

Published in National conference proceedings

  1. S.Kumaravel, B.Venkataramani, Ajit Randhir, and Ramakrishna Chowtri, A Novel Fully Differential Folded Cascode Operational Transconductance Amplifier, VDAT July 7-9 2011, Pune.
  2.  S.Kumaravel, B.Venkataramani and Akila M, Behavioural Analysis of Clock Jitter Effects in Continuous Time Sigma Delta Modulator, VDAT July 7-9, 2011, Pune.
  3. S.Kumaravel, B.Venkataramani and Aryam Gupta, VLSI Implementation of Gm-C filter using Modified Nauta OTA with double CMOS pair, Accepted for presentation at IEEE RAICS Sep 22-24, 2011, Trivandrum
  4. N. Sreekanth Babu, S. Ramasamy, B.Venkataramani, “Design of high performance current steering DAC using pattern search algorithm” , Proc. Of VLSI design and test symposium VDAT 2007, Aug 2007, Calcutta, India, pp. 120-129
  5. S. Ramasamy, B.Venkataramani, N. Sreekanth Babu, “Design and implementation of 14 bit 200Msps current steering DAC using Gm/Id method”, Proc. Of VLSI design and test symposium VDAT 2007, Aug 200, Calcutta, India, pp.105 -113
  6. V. Amudha, B.Venkataramani, J.Karthick and C. Praveen, “ SOC implementation of the neural network based isolated word recognition”, proceedings of VDAT 2006, pp. 130-138.
  7. G. Seetharaman, B. Venkataramani and G. Lakshminarayanan, “Design and FPGA implementation of wavepipelined image block encoders using 2D-DWT”, Proc. of VLSI design and test symposium VDAT 2005, Aug 2005, Bangalore, pp 12-20
  8. G. Seetharaman, B. Venkataramani and G.Lakshminarayanan, Design and FPGA implementation of wavepipelined distributed arithmetic based filters, Proceedings of VLSI Design & Test workshop VDAT04, pp. 216-220, August 2004, Mysore
  9. G. Lakshminarayanan, B. Venkataramani, M. Yousuff Shariff, T. Rajavelu and M. Ramesh, “Self tuning circuit for FPGA based wavepipelined multipliers”, Proceedings of VLSI Design & Test workshop VDAT04, pp. 93-101, August 2004, Mysore
  10. J.Senthil Kumar , G.Sriram, G.Lakshminarayanan , B.Venkataramani, “ Design and Implementation of FPGA based Fast Multipliers with Optimum Placement & Routing Using Structure Organizer, National Conference on VLSI design & Testing, PSG College of Technology, Coimbatore, 21-22 February, 2003.
  11. U. Uma Maheswari, H. Anand, S. Ramasamy,K Subramanyam, B.Venkataramani, G. Lakshminarayanan, “Performance evaluation of various schemes for FPGA implementation of 2D- DWT , National Conference on VLSI design & Testing, PSG College of Technology, Coimbatore, 21-22 February, 2003
  12. B.Venkataramani, “High Performance DSP circuits using FPGAs”, Workshop on 'DSP/FPGA technologies' , CEERI Chennai, June 24-25 2002
  13. M.C.Sundar, A.Senthil Kumar, B.Venkataramani, M. Bhaskar, “ Implementation Of FPGA Based Image Processing System With Lifting Wavelet Transform, Proc. Of National workshop on Computer Vision, Graphics and Image Processing, WVGIP 2002, TCE, Madurai, Feb 2002, pp 45-50
  14. K.Balaji, B.Venkataramani, M.Bhaskar, G. Lakshminarayanan, Enhancing the Performance of the TI DSP systems with FPGAs, Texas Instruments DSPFEST-2001, Bangalore
  15. B. Venkataramani, S.K. Bose, K.R. Srivathsan, Computation of Queuing delays of a non-preemptive MMPP/D/1 priority system, proc. National Communications Conf. 1997, I.I.T., Madras, India, 1997 pp. 12-16.
  16. B. Venkataramani, S.K. Bose, K.R. Srivathsan, Queuing analysis of a non-preemptive MMPP/D/1/K priority system, Pro. National Communications Conf. 1996, I.I.T., Bombay, India, February 1996, pp. 243-246.